(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating dual-metal transistors in the fabrication of integrated circuits.
(2) Description of the Prior Art
For sub-0.1 xcexcm CMOS technology, there are a number of issues. The choice of gate dielectric is one issue that will not be addressed here. Other issues related to the gate stack include:
1) Metal gates are needed to replace conventional polysilicon gates in order to reduce poly depletion effects. Depletion effects translate to a reduction in the electric field across the gate dielectric (Eox) and hence inversion charge density; that is, lower drive current. The effect will become more pronounced with smaller gate geometries due to thinner gate oxide, which translates to a higher gate oxide capacitance. This results in a non-negligible depletion capacitance in the polysilicon gate as well as the silicon channel.
2) Metal gates are needed to replace conventional salicided polysilicon gates. Low gate resistance is difficult to achieve with conventional salicide technology due to the conflicting demands of good junction integrity and low gate resistance. On the source/drain, a silicide thickness of less than 20 nanometers is required when gate geometries reach below 70 nm for low specific contact resistivity. On the other hand, it is expected that the silicide thickness on the gate must be at least 45 nm in order to attain a sheet resistance of less than 5 ohms/sq for low signal propagation delay.
3) Different metals are needed for n+ and p+ gates due to gate work function considerations in order to achieve symmetrically low threshold voltages (for low-power devices such as portables) for the NFETs and PFETs.
It is desired to provide a process to address these various concerns.
U.S. Pat. No. 6,001,698 to Kuroda discloses a process for forming CMOS gates using an inverse gate process. U.S. Pat. No. 5,786,256 to Gardner et al shows an inverse polysilicon gate process. U.S. Pat. Nos. 6,114,206 to Yu and 6,184,083 to Tsunashima et al disclose dummy gate polysilicon gate processes. U.S. Pat. No. 6,066,533 to Yu shows a dual metal gate process. U.S. Pat. No. 6,033,963 to Huang et al discloses a metal gate process using a dummy gate. U.S. Pat. No. 5,731,239 to Wong et al teaches a polysilicon gate process. U.S. Pat. No. 5,447,874 to Grivna et al discloses a two layer metal gate. Co-pending U.S. patent application Ser. No. 09/797,555 to N. C. Hwei et al discloses another method of forming dual metal gates that address the issues described herein above.
Accordingly, a primary object of the invention is to provide a process for forming metal gates for CMOS transistors in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming dual-metal gate CMOS transistors in the fabrication of integrated circuits.
In accordance with the objects of the invention, a method for forming a dual-metal gate CMOS transistors is achieved. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by isolation regions. A pad oxide layer is formed overlying the semiconductor substrate in each of the active areas. A nitride layer is deposited overlying the pad oxide layer. The nitride layer is patterned to form a first dummy gate in each of the active areas. Ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates. Thereafter, the source/drain regions are silicided. The second dummy gates and spacers are removed. A first gate dielectric layer is deposited overlying the substrate and silicided source/drain regions. A first diffusion barrier layer is deposited overlying the first gate dielectric layer. A first metal layer is deposited overlying the first diffusion barrier layer. The first metal layer, first diffusion barrier layer, and the first gate dielectric layer are patterned to form a first metal gate in one of the NMOS and PMOS active areas. An oxide layer is deposited overlying the substrate and the first metal gate. The oxide layer is polished back to the metal gate. A via is opened through the oxide layer to the substrate in the other one of the NMOS and PMOS areas. A second gate dielectric layer is deposited within the via opening. A second diffusion barrier layer is deposited overlying the second gate dielectric layer. A second metal layer is deposited overlying the second diffusion barrier layer and polished back to the oxide layer to form a second metal gate in the other one of the NMOS and PMOS areas to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.